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HUF75617D3, HUF75617D3S
Data Sheet December 2001
16A, 100V, 0.090 Ohm, N-Channel, UltraFET(R) Power MOSFETs Packaging
JEDEC TO-251AA JEDEC TO-252AA
Features
* Ultra Low On-Resistance - rDS(ON) = 0.090, VGS = 10V * Simulation Models - Temperature Compensated PSPICE(R) and SABERTM Electrical Models - Spice and SABER Thermal Impedance Models - www.fairchildsemi.com * Peak Current vs Pulse Width Curve * UIS Rating Curve
SOURCE DRAIN GATE GATE DRAIN (FLANGE) SOURCE
DRAIN (FLANGE)
HUF75617D3
HUF75617D3S
Symbol
D
Ordering Information
PART NUMBER HUF75617D3 PACKAGE TO-251AA TO-252AA BRAND 75617D 75617D
G
HUF75617D3S
S
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUF75617D3ST. TC = 25oC, Unless Otherwise Specified HUF75617D3, HUF75617D3S UNITS V V V A A
Absolute Maximum Ratings
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC = 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg NOTE: TJ = 25oC to 150oC.
100 100 20 16 11 Figure 4 Figures 6, 14, 15 64 0.43 -55 to 175 300 260
W W/oC
oC oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html For severe environments, see our Automotive HUFA series. All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
(c)2001 Fairchild Semiconductor Corporation
HUF75617D3 Rev. B
HUF75617D3
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS ID = 250A, VGS = 0V (Figure 11) VDS = 95V, VGS = 0V VDS = 90V, VGS = 0V, TC = 150oC Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RJC RJA TO-251, TO-252 2.34 100
oC/W oC/W
TC = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
100 -
-
1 250 100
V A A nA
IGSS
VGS = 20V
VGS(TH) rDS(ON)
VGS = VDS, ID = 250A (Figure 10) ID = 16A, VGS = 10V (Figure 9)
2 -
0.080
4 0.090
V 3/4
SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) 570 125 20 pF pF pF Qg(TOT) Qg(10) Qg(TH) Qgs Qgd VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 50V, ID = 16A, Ig(REF) = 1.0mA (Figures 13, 16, 17) 31 18 1.3 2.7 6.4 39 22 1.6 nC nC nC nC nC tON td(ON) tr td(OFF) tf tOFF VDD = 50V, ID = 16A VGS = 10V, RGS = 12 (Figures 18, 19) 6 35 44 28 60 108 ns ns ns ns ns ns
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage SYMBOL VSD ISD = 16A ISD = 7A Reverse Recovery Time Reverse Recovered Charge trr QRR ISD = 16A, dISD/dt = 100A/s ISD = 16A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 1.00 80 170 UNITS V V ns nC
(c)2001 Fairchild Semiconductor Corporation
HUF75617D3 Rev. B
HUF75617D3 Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
18 15
ID, DRAIN CURRENT (A)
1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC)
12 9 6 3 0 25
VGS = 10V
50
75
100
125
150
175
TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
2 1 THERMAL IMPEDANCE ZJC, NORMALIZED
DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM
0.1 t1 t2 NOTES: DUTY FACTOR: D = t1 /t2 PEAK TJ = PDM x ZJC x RJC + TC 10 -3 10-2 t, RECTANGULAR PULSE DURATION (s) 10 -1 10 0 101
SINGLE PULSE 0.01 10 -5 10-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
300 200
IDM, PEAK CURRENT (A)
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 175 - TC 150 VGS = 10V
100
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
FIGURE 4. PEAK CURRENT CAPABILITY
(c)2001 Fairchild Semiconductor Corporation
HUF75617D3 Rev. B
HUF75617D3 Typical Performance Curves
200 100 ID, DRAIN CURRENT (A)
(Continued)
100 IAS , AVALANCHE CURRENT (A) SINGLE PULSE TJ = MAX RATED TC = 25oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BV DSS - VDD) +1]
10
100s 1ms
10
STARTING TJ = 25oC
1
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON)
10ms
STARTING TJ = 150oC
0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 200
1 0.001
0.01
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
30 25
ID, DRAIN CURRENT (A)
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V
ID, DRAIN CURRENT (A)
30 25 VGS = 10V VGS = 6V 20 15 10 5 0 0 1 2 3 VDS, DRAIN TO SOURCE VOLTAGE (V) 4 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC VGS = 5V
20 15 10 5 TJ = 25oC 0 2 3 4 5 6 TJ = 175oC TJ = -55oC
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
3.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE
1.2 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX NORMALIZED GATE THRESHOLD VOLTAGE VGS = VDS, ID = 250A
2.5
1.0
2.0
1.5
0.8
1.0 VGS = 10V, ID = 16A 0.5 -80 -40 0 40 80 120 160 200 0.6 -80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
(c)2001 Fairchild Semiconductor Corporation
HUF75617D3 Rev. B
HUF75617D3 Typical Performance Curves
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A
(Continued)
2000 1000 C, CAPACITANCE (pF) VGS = 0V, f = 1MHz
1.1
CISS = CGS + CGD COSS CDS + CGD 100 CRSS = CGD
1.0
0.9 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC)
10 0.1
1.0
10
100
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 50V 8
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
6 WAVEFORMS IN DESCENDING ORDER: ID = 16A ID = 10A ID = 4A
4
2
0
0
5
10 15 Qg , GATE CHARGE (nC)
20
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
(c)2001 Fairchild Semiconductor Corporation
HUF75617D3 Rev. B
HUF75617D3 Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS RL VDD VDS VGS = 20V VGS
+
Qg(TOT)
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 10V
DUT Ig(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
DUT RGS
VDD 0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. SWITCHING TIME WAVEFORM
(c)2001 Fairchild Semiconductor Corporation
HUF75617D3 Rev. B
HUF75617D3 PSPICE Electrical Model
.SUBCKT HUF75617d3 2 1 3 ;
CA 12 8 9.9e-10 CB 15 14 1.0e-9 CIN 6 8 5.4e-10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD
10
rev 24May 2000
LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + EBREAK MWEAK MMED MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 22 RVTHRES 14 IT VBAT + 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 17 18 DBODY DRAIN 2 RSLC1 51 ESLC 50
RSLC2
5 51 ESG 6 8 + LGATE GATE 1 RLGATE EVTEMP RGATE + 18 22 9 20 EVTHRES + 19 8 6 -
IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 5.24e-9 LSOURCE 3 7 4.25e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 3.9e-2 RGATE 9 20 2.45 RLDRAIN 2 5 10 RLGATE 1 9 52.4 RLSOURCE 3 7 42.5 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 3.2e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*32),3.5))} .MODEL DBODYMOD D (IS = 6.0e-13 RS = 11.0e-3 XTI = 4.5 TRS1 = 1.1e-3 TRS2 = 7.1e-6 CJO = 6.5e-10 TT = 4.1e-8 M = 0.54) .MODEL DBREAKMOD D (RS = 5.6e- 1TRS1 = 8.0e- 4TRS2 = 3.0e-6) .MODEL DPLCAPMOD D (CJO = 7.0e-1 0IS = 1e-3 0M = 0.89 N = 10) .MODEL MMEDMOD NMOS (VTO = 3.10 KP = 3 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.45) .MODEL MSTROMOD NMOS (VTO = 3.64 KP = 42 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.68 KP = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 24.5) .MODEL RBREAKMOD RES (TC1 = 1.05e- 3TC2 = -5.0e-7) .MODEL RDRAINMOD RES (TC1 = 1.20e-2 TC2 = 3.00e-5) .MODEL RSLCMOD RES (TC1 = 3.2e-3 TC2 = 1.0e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2.2e-3 TC2 = -9.0e-6) .MODEL RVTEMPMOD RES (TC1 = -2.4e- 3TC2 = -1.8e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -5.9 VOFF= -3.1) VON = -3.1 VOFF= -5.9) VON = -0.6 VOFF= 0.5) VON = 0.5 VOFF= -0.6)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
(c)2001 Fairchild Semiconductor Corporation
+
EBREAK 11 7 17 18 117.8 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1
RDRAIN 21 16
HUF75617D3 Rev. B
HUF75617D3 SABER Electrical Model
REV 24 May 2000 template huf75617d3 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 6.0e-13, rs = 11.0e-3, xti = 4.5, trs1 = 1.1e-3, trs2 = 7.1e-6, cjo = 6.5e-10, tt = 4.1e-8, m = 0.54) dp..model dbreakmod = (rs = 5.6e-1, trs1 = 8.0e-4, trs2 = 3.0e-6) dp..model dplcapmod = (cjo = 7.0e-10, isl = 10e-30, m = 0.89, nl = 10) m..model mmedmod = (type=_n, vto = 3.10, kp = 3, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.64, kp = 42, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.68, kp = 0.02, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.9, voff = -3.1) DPLCAP 5 sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3.1, voff = -5.9) 10 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.6, voff = 0.5) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -0.6) RSLC1 c.ca n12 n8 = 9.9e-10 c.cb n15 n14 = 1.0e-9 c.cin n6 n8 = 5.4e-10 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1.0e-9 l.lgate n1 n9 = 5.24e-9 l.lsource n3 n7 = 4.25e-9
GATE 1 RLGATE CIN LGATE ESG + EVTEMP RGATE + 18 22 9 20 6 MSTRO 8 6 8 EVTHRES + 19 8 51 RSLC2 ISCL 50 RDRAIN 21 16 MWEAK MMED EBREAK + 17 18 RSOURCE RLSOURCE S1A 12 13 8 S1B CA 13 + EGS 6 8 S2A 14 13 S2B CB + EDS 5 8 8 RVTHRES 14 IT VBAT + 22 15 17 RBREAK 18 RVTEMP 19 DBODY DBREAK 11
LDRAIN DRAIN 2 RLDRAIN
LSOURCE 7
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -5.0e-7 res.rdrain n50 n16 = 3.9e-2, tc1 = 1.20e-2, tc2 = 3.00e-5 res.rgate n9 n20 = 2.45 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 52.4 res.rlsource n3 n7 = 42.5 res.rslc1 n5 n51 = 1e-6, tc1 = 3.2e-3, tc2 = 1.0e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.2e-2, tc1 = 1e-3, tc2 = 1e-6 res.rvtemp n18 n19 = 1, tc1 = -2.4e-3, tc2 = 1.8e-6 res.rvthres n22 n8 = 1, tc1 = -2.2e-3, tc2 = -9.0e-6 spe.ebreak n11 n7 n17 n18 = 117.8 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1 equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/32))** 3.5)) } }
SOURCE 3
(c)2001 Fairchild Semiconductor Corporation
HUF75617D3 Rev. B
HUF75617D3 SPICE Thermal Model
REV 24 May 2000
th JUNCTION
HUF75617D CTHERM1 th 6 1.00e-3 CTHERM2 6 5 4.00e-3 CTHERM3 5 4 4.00e-3 CTHERM4 4 3 3.60e-3 CTHERM5 3 2 7.00e-3 CTHERM6 2 tl 5.00e-2 RTHERM1 th 6 1.59e-2 RTHERM2 6 5 3.96e-2 RTHERM3 5 4 1.12e-1 RTHERM4 4 3 4.27e-1 RTHERM5 3 2 6.45e-1 RTHERM6 2 tl 7.00e-1
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model HUF75617D template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 1.00e-3 ctherm.ctherm2 6 5 = 4.00e-3 ctherm.ctherm3 5 4 = 4.00e-3 ctherm.ctherm4 4 3 = 3.60e-3 ctherm.ctherm5 3 2 = 7.00e-3 ctherm.ctherm6 2 tl = 5.00e-2 rtherm.rtherm1 th 6 = 1.59e-2 rtherm.rtherm2 6 5 = 3.96e-2 rtherm.rtherm3 5 4 = 1.12e-1 rtherm.rtherm4 4 3 = 4.27e-1 rtherm.rtherm5 3 2 = 6.45e-1 rtherm.rtherm6 2 tl = 7.00e-1 }
RTHERM3 CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
(c)2001 Fairchild Semiconductor Corporation
HUF75617D3 Rev. B
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Rev. H4

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